1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method thereof. More particularly, the present invention relates to a semiconductor device having a contact hole and to a manufacturing method thereof.
2. Description of the Background Art
A conventional semiconductor device having a contact hole and manufacturing method thereof will be described.
FIG. 51 is a schematic cross section showing a structure of a semiconductor device in accordance with a first prior art example. Referring to FIG. 51, an MOS (Metal Oxide Semiconductor) transistor 10 is formed on a surface of a semiconductor substrate 1.
MOS transistor 10 includes a pair of source/drain regions 3, 3, a gate insulating layer 5, and a gate electrode layer 7. The pair of source/drain regions 3, 3 are formed spaced by a prescribed distance at the surface of semiconductor substrate 1. Gate electrode layer 7 is formed on the surface of semiconductor substrate 1 sandwiched by the pair of source/drain region 3, 3, with gate insulating layer 5 interposed.
An interlayer insulating layer 11 is formed entirely over the surface of semiconductor substrate 1 to cover MOS transistor 10. In interlayer insulating layer 11, a contact hole 525 reaching a part of the surface of source/drain region 3 is formed. A conductive layer 521 such as an electrode is formed to be electrically connected to the source/drain region 3 through contact hole 525.
The method of manufacturing a semiconductor device in accordance with the first prior art example will be described.
FIGS. 52 to 56 are schematic cross sections showing, in order, the steps of manufacturing the semiconductor device in accordance with the first prior art example. Referring to FIG. 52, on the surface of semiconductor substrate 1, gate insulating layer 5 and conductive layer 7a are formed stacked on one another. On conductive layer 7a, a resist pattern 531a is formed by photolithography. By using resist pattern 531a as a mask, conductive layer 7a and gate insulating layer 5 are etched. Thereafter, resist pattern 531a is removed.
Referring to FIG. 53, by this etching, a gate electrode layer 7 having a desired shape is formed. Thereafter, by using gate electrode layer 7 and an element isolating insulating layer (not shown) as a mask, ion implantation or the like is performed to semiconductor substrate 1. Consequently, a pair of source/drain regions 3, 3 are formed spaced by a prescribed distance from each other on the surface of semiconductor substrate 1 on both sides of a region immediately below the gate electrode layer 7. By the pair of source/drain regions 3, 3, gate insulating layer 5 and gate electrode layer 7, an MOS transistor 10 is provided.
Referring to FIG. 54, interlayer insulating layer 11 is formed to cover MOS transistor 10.
Referring to FIG. 55, on interlayer insulating layer 11, a resist pattern 531b is formed by normal photolithography technique. Resist pattern 531b has a hole pattern 531b.sub.1 above the source/drain regions 3. By using resist pattern 531b as a mask, anisotropic etching is performed on interlayer insulating layer 11. Thereafter, resist pattern 531b is removed.
Referring to FIG. 56, by this etching, a contact hole 524 reaching the source/drain region 3 is formed in interlayer insulating layer 11. Conductive layer 521 is formed on interlayer insulating layer 11 to be electrically connected to source/drain region 3 through contact hole 525, and thus the semiconductor device shown in FIG. 51 is completed.
The semiconductor device in accordance with the first prior art example suffers from the following problems. Generally, when the degree of integration of the DRAM (Dynamic Random Access Memory) is increased, memory size is unavoidably reduced. As the memory size is reduced, the pitch L.sub.1 between word line 7 shown in FIG. 51 is also reduced unavoidably. Accordingly, the distance L.sub.2 between the word lines is also reduced. Meanwhile contact hole 525, which is formed by the conventional photolithography as shown in FIGS. 55 and 56 has an opening diameter L.sub.3, which cannot be reduced to be smaller than a prescribed limit, because of restriction in photolithography.
Under the circumstances, it may be possible that the center (denoted by chain dotted line Q--Q) of hole pattern 531b.sub.1 of resist pattern 531b is shifted to the left or the right in the step of FIG. 55, for example, because of registration error or dimensional error of the mask in photolithography.
FIG. 57 shows a state in which the center of the hole pattern 531b.sub.1 is deviated. If the resist pattern 531b in this state is used as a mask and interlayer insulating layer 11 is etched, contact hole is formed as shown in FIG. 58. More specifically, gate electrode layer 7 is exposed at the sidewall of contact hole 525.
If the conductive layer 521 is formed in the state shown in FIG. 58, conductive layer 521 and gate electrode layer 7 would be electrically short-circuited as shown in FIG. 59.
In order to prevent this short-circuiting, the following method is possible.
FIGS. 60 and 61 are schematic cross sections showing the steps of the method of preventing short-circuit.
First, referring to FIG. 60, in order to cover the surface of the gate electrode layer 7 exposed at the sidewall of contact hole 525, an insulating layer 601a is formed. Thereafter, etching by anisotropic RIE (Reactive Ion Etching) is performed on insulating layer 601a.
Referring to FIG. 61, by this etching, sidewall insulating layer 601 is formed in self-aligned manner to cover the exposed surface of gate electrode layer 7 and the sidewall of contact hole 525.
By providing sidewall insulating layer 601 in this manner, the surface of gate electrode layer 7 can be covered, and hence short-circuit between the conductive layer and gate electrode layer 7 can be prevented.
However, control of etching of insulating layer 601a shown in FIGS. 60 and 61 is not easy. Therefore, even by this method, part of the gate electrode layer 7 (P portion) may be exposed from sidewall insulating layer 601, as shown in FIG. 62.
Further, even when the surface of gate electrode layer 7 is completely covered by sidewall insulating layer 601 as shown in FIG. 61, the thickness of the sidewall insulating layer 601 covering gate electrode layer 7 is thin. Therefore, there is a high possibility that a current flows through the conductive layer and gate electrode layer 7 through sidewall insulating layer 601, because of the potential difference between the conductive layer and gate electrode layer 7 generated during the operation.
A method has been proposed, for example, in Japanese Patent Laying-Open No. 6-260442 which solves the above described problem. This method will be described as a second prior art example.
FIGS. 63 to 69 are schematic cross sectional views showing, in order, the method of manufacturing the semiconductor device in accordance with the second prior art example. Referring to FIG. 63, on a surface of a semiconductor substrate 1 separated by element isolating insulating layer 241, an MOS transistor 10 constituted by a pair of source/drain regions 3, gate insulating layer 5 and gate electrode layer 7 is formed. On the entire surface of semiconductor substrate 1, an interlayer insulating layer 11 formed, for example, of silicon oxide film is formed to cover MOS transistor 10. On interlayer insulating layer 11, a polycrystalline silicon layer 13a having different etch property than insulating layer 11 is formed. On polycrystalline silicon layer 13a, silicon oxide film 15 having the same etch property as interlayer insulating layer 11 is formed.
Referring to FIG. 64, a resist pattern 371a is formed on silicon oxide film 13, by using resist pattern 371a as a mask, anisotropic etching is performed on silicon oxide film 15. Thus, an opening 23 is provided in silicon oxide film 15. Thereafter, resist pattern 371a is removed.
Referring to FIG. 65, a silicon oxide film 17a is formed entirely over the surface to cover inner wall surface of opening 23. Anisotropic etching is performed on the entire surface of silicon oxide film 17a.
Referring to FIG. 66, by the anisotropic etching, a sidewall insulating layer 17 which is of silicon oxide film, is left on the sidewall of opening 23. By using silicon oxide film 15 and sidewall insulating layer 17 as a mask, anisotropic etching is formed on polycrystalline silicon layer 13a.
Referring to FIG. 67, by the etching, opening 25 is formed in polycrystalline silicon layer 13a. By using polycrystalline silicon layer 13a having opening 25 as a mask, anisotropic etching is performed on interlayer insulating layer 11.
Referring to FIG. 68, by the anisotropic etching, a contact hole 727 having the same opening diameter D.sub.3 as opening 25 of polycrystalline silicon layer 23a is formed in interlayer insulating layer 11.
By the anisotropic etching, silicon oxide film 15 and sidewall insulating layer 17 having the same etching property as interlayer insulating layer 11 are removed.
Referring to FIG. 69, a polycrystalline silicon layer 13b is formed on polycrystalline silicon layer 13a to fill contact hole 727 and to be electrically connected to source/drain regions 3. Thereafter, by common photolithography and etching, polycrystalline silicon layers 13b and 13a are etched successively, and thus a conductive layer 13 having a desired shape is provided.
According to the method described above, in the step shown in FIG. 66, a sidewall insulating layer 17 is formed on the sidewall of opening 23. Then, using silicon oxide film 15 and sidewall insulating film 17 as a mask, etching is performed on polycrystalline silicon layer 13. Therefore, the opening diameter of opening 25 shown in FIG. 67 can be made smaller than the minimum processing dimension of photolithography. Accordingly, the opening diameter D.sub.3 of contact hole 727 in interlayer insulating layer 11 which is etched using the polycrystalline silicon layer 13a having opening 25 as a mask can be made smaller than the minimum possible processing dimension of photolithography.
Therefore, even when the space between gate electrode layers 7 is reduced due to increased degree of integration, short-circuit between conductive layer 13 and gate electrode layer 7 can be prevented.
However, in the second prior art example, conductive layer 13 shown in FIG. 69 is a bit line, and there is a problem that manufacturing becomes complicated when a storage node is to be formed on bit line 13. This problem will be described in detail in the following.
FIGS. 70 to 74 are schematic cross sections showing the steps for forming a storage node on the bit line in the second prior art example. Referring to FIG. 70, as in the step shown in FIG. 63, interlayer insulating layer 711 formed of silicon oxide film, polycrystalline silicon layer 713a and silicon oxide film 715 are formed successively to cover bit line 13.
Then, referring to FIG. 71, as in the step shown in FIG. 64, resist pattern 771a is formed on silicon oxide film 715, and using resist pattern 771a as a mask, silicon oxide film 715 is etched. Thus opening 723 is formed in silicon oxide film 715. Thereafter, resist pattern 771 is removed.
Referring to FIG. 72, as in the step shown in FIG. 65, silicon oxide film 717a is formed on the entire surface to cover inner wall surface of opening 723. Anisotropic etching is performed on the entire surface of silicon oxide film 717a.
Referring to FIG. 73, as described in the step shown in FIG. 66, by this etching, sidewall insulating layer 717 is formed on the sidewall of opening 723. By using silicon oxide film 715 and sidewall insulating layer 717 as a mask, anisotropic etching is performed on polycrystalline silicon film 713a.
Referring to FIG. 74, as described in the step shown in FIGS. 67 and 68, by the anisotropic etching, an opening is formed in polycrystalline silicon film 713a. By using polycrystalline silicon film 713a as a mask, anisotropic etching is performed on insulating layers 711 and 11. Thus a contact hole 727a for a storage node is formed in insulating layers 711 and 11.
Silicon oxide film 715 and sidewall insulating layer 717 shown in FIG. 73 are removed when insulating layers 711 and 11 are etched.
Thereafter, a storage node is formed to be electrically connected to source/drain region 3 of MOS transistor 10 through contact hole 727a.
By repeating the steps of forming contact hole 727 for the bit lines, contact hole 727a for the storage node can be formed with its opening diameter made smaller than the minimum possible processing dimension of photography.
However, when contact holes 727a for the storage nodes are to be formed by this method, it is necessary to repeat the steps of forming contact hole 727 for the bit line, and hence the number of steps of manufacturing becomes unavoidably large.